Full Circuit Ltd, Chippenham, Wiltshire
Design Consultancy (my company)
August 1996 to date
Technically Responsible for :-
2013. A complete rewrite, in 3 weeks, of ARM SBC software with Ethernet IP stack together with real time ADC sampling. Software included debug routines which later proved their worth again in prototype setup.
2013. Feasibility study on minimum changes/practicality of ROM working voltage change (50V to 12V). Transformer redesign and component selection. System simulation leading to VHDL changes to suit new design. Prototype testing.
2012/2013. Design, hardware analysis and EOLA (Enviromental Operating Limits Analysis) reviewing.
2010/11. Rail signalling relay output module. Floating outputs, switch mode based, SIL4 design.
Responsible for concept, circuitry, transformer design, VHDL safety concepts, parts of the VHDL coding/design
2010. Rail coded input contact proving module. Transformer design (400/800Hz). Manchester encoded signal
for contact proving. SIL4 (safety) design. Improved and maximised wetting and reliability. Well defined, testable and proved closed/open loop impedances.
2009/10. Rail points machine direct drive module. AC input, forward and reverse outputs, 120Vdc, 28A.
Safety concepts, circuitry design including heatsinking. VHDL safety concepts and design.
2009. Jointless Track Circuit Unit oscillator problem study and retro-fitted fix design.
2009. LED signal lamp replacement. Revised yellow variant analysis.
2008. Rail signalling input and signal module outline concepts and design.
2007. Rail SSI TFM EMI issues study and analysis. Finding the root of EMI induced problem and designing a solution.
2006. Rail Joint-Less Track Circuit set-up and maintenance tool. Rail inductance measurement plus other diagnostics.
Hand-held, battery powered, graphic display and keypad. Self-testing and calibrating. PIC DSP processor based. Gyrator based narrow band
filters. Responsible for whole design, concept, circuitry, mechanic packaging, software, VHDL for cpld’s and PCB layout. Plus build of 10 units.
2005. Rail safety sensor of isolated current and voltage. Design, analysis, modelling and prototyping.
2005. LED signal lamp replacement. Blue variant analysis.
2005. Low cost PIC based X10 mains signalling to/from RS232, including mechanical design concept.
Novel I/O filter design, low cost, high performance. Output designed for EN50065.
2004. PIC based interface. Inputs: switches and signals. Outputs: relay drives and signals. Software
State Machine with switch debounce, timing functions and watchdog for robust operation. Power usage minimised.
2004. High frequency Class B power amplifier (0dB 1MHz). Tuned loop load via up to 2.5km of cable.
Stable under all conditions. Design achieved distortion well below 0.01% specification.
2003. FSK Loop modem. Designed with filters using Gyrator and NFDR versions of LC ladders for stability,
defined characteristics, and long available life expectancy. CPLD used for FSK generation and decoding. CPLD also for VME interface.
2003. 115V 400Hz and 28Vdc PSU for LED Anti-Collision light. Energy storage to spread flash surge. Constant
current output regulation. Extremely accurate flash time to ensure synchronisation between separate units.
2002. Main and display PSUs running off ship's battery and to meet EMC requirements.
2001. LED signal lamp replacement. 110V input, sinewave current load. DC current output, temperature compensated
to give constant light level. LED PCB thermal design and analysis.
2001. LED lamp close tolerance constant current regulator. The impossible of 4 regulators, one matching a
temperature compensation curve, over 70W dissipation, all in a 20x30x12mm volume (in surface mount not hybrid).
2000. VHDL IP, design and test, for replacement of obsolete uart/timer ic with cplds. Including difficult mechanical
and layout design to fit in 18 pin DIL footprint.
2000. FMECA of VLC5 processor based vital module.
2000. Investigation into CPLD, FPGA, ASIC, etc. replacements for TMS9995 processor and TMS9902 UART, including costings.
2000. Analysis of VLM software performance, identifying bottlenecks. Streamlined code to give factor of 2 processing improvement.
Analysis of hardware to define best option for future speed improvements.
1999. Analysis of algorithm/hardware problem which was causing infrequent but costly failures. Re-designed algorithm to be stable
and more noise immune. Analysed worst case noise disturbance to prove recovery in time allowed.
1999. Creation of two C++ classes (MS Visual C++) to add Monte Carlo and Worst Case analysis to spice simulation program.
1999. Analysis of Oslo railway environment and GPOM to track down failures only occurring once every two months (extensive site tests and lab measurements).
1999. Re-design of parts of a laser and camera 3D scanner to correct problems (surface mount plus tight space constraints). Design of new 3 channel video
digitiser for SBC or PC, variable resolution in width and height. Schematic and detailed layout guidelines (IC placement, pin allocation, general routing areas, 0V connections and
1998. Design analysis and simulation of inductive loop system (power amp, PLL decoding FSK). Creation of (spice ac) model of switched capacitor filters.
1998. Design analysis identifying the cause of failures and the design of solutions. Various areas of train equipment (ATO and ATP) covering life prediction, PLL,
comms, filters, relays, opto-isolators, and general digital.
1997/8. Design of calibration equipment with low drift (0.1%) yet to take high power pulses (3kW). Other parts with even lower drift (125ppm but less power). Design of
dual slope ADC and precision temperature measurement.
1997. Analysis of FS2600 track circuit to develop fixed set-up method for Australia.
1996/7. Design of FS2700 Track Circuit filter element between transmitter (signal generator) and track to make workable track circuit. Simulation of FS2700 performance
(including EMI) on railway. Technical support for other FS2700 component design teams.
Westinghouse Signals, Chippenham, Wiltshire, UK
Railway Signaling Equipment
October 1982 to July 1996
Technically Responsible for :-
1996. All system and outline design for FS2700 Track Circuit including new features of heterodyne via lookup table for narrow and site selectable filter (pre complex FFT). The most difficult
analogue and digital design areas. Designs include; switch mode psu, output matching filter, safety proving circuit.
1996. Outline design (which reused a lot of FS2600) for FS2550 Track Circuit . Part of analogue design and the new safety proving circuit (digital). One patent
1993 - 1995. All system and outline design for FS2600 Track Circuit. The most difficult analogue areas including input filter, total 21st order, with heterodyne stage (pre FFT).
Most of the system simulation and the new features. Presented these innovations in a joint paper with a colleague at Aspect 95
and 2 other venues.
1993. General Purpose Output Module outline design to solve extremely arduous requirements. All detailed design including embedded processor, A/D, output stages,
using mosfets for PWM dimming, with hall effect current sensors.
1992. Generation of new track circuit ideas. Two patents
taken out. On going, staged development.
1988 - 1992. Westrace Interlocking. All parallel output, ac-dc mosfets, and input design (fail-safe). Two
taken out (3 for the entire system). Master fail-safe output design.
1987. Self test software using loop back and software UART. Site tests in Hong Kong.
1982 - 1986. FS2000 Automatic Train Protection. Embedded processor design, added innovation of fault reporting using NV ram and mini printer. Software and hardware of site test box, performing FFT,
with LCD display of results. Technical support for (successful) sales team in Singapore.